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US 2011/0215835 A1Published application
Quad state logic design methods, circuits and systems
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.
Claims1
A circuit for compressing a pair of first and second digital input signals into a quad state output signal comprising,
- a decode circuit having inputs for receiving the pair of first and second digital input signals and outputs for outputting control signals,
- a first switch having an input coupled to a first voltage level, an input coupled to a first one of the control signals and an output,
- a second switch having an input coupled to a second voltage level, an input coupled to a second one of the control signals and an output,
- a third switch having an input coupled to a third voltage level, an input coupled to a third one of the control signals and an output,
- a fourth switch having an input coupled to a fourth voltage level, an input coupled to a fourth one of the control signals and an output, and;
- a connection formed between the outputs of the first, second, third and fourth switches and the quad state output signal.
3 more elements
Dependencies are inferred from the claim text.