Apparatus of low power, area efficient finfet circuits and method for implementing the same
OwnerMichael C. Wanginventor
Life of this patent
Estimating the term…
Abstract
A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.
Claims20
A FinFET majority gate comprising:
- at least three inputs;
- an output;
- a pull-up network having at least three P-FinFETs connected in series, the pull-up network coupled to the output through one of the at least three P-FinFETs;
- and
- a pull-down network having at least three N-FinFETs connected in series, the pull-down network coupled to the output through one of the at least three N-FinFETs.
A FinFET MUX comprising:
- at least two data inputs;
- a selection input;
- an output;
- a pull-up network having at least two P-FinFETs connected in series, the pull-up network coupled to the output through one of the at least two P-FinFETs;
- and
- a pull-down network having at least two N-FinFETs connected in series, the pull-down network coupled to the output through one of the at least two N-FinFETs.
A computer readable storage medium for generating a digital circuit comprising an output, the computer readable storage medium carrying one or more sequences of one or more instructions which, when executed by one or more processors, cause the one or more processors to perform the computer-implemented steps of:
- constructing a logic expression in OR-AND form corresponding to the output of the digital circuit;
- constructing a logic expression in OR-AND form corresponding to the complement of the output of the digital circuit;
- mapping the logic expressions into a CMOS circuit;
- merging two parallel NMOS transistors of the CMOS circuit into a N-FinFET;
- and
- merging two parallel PMOS transistors of the CMOS circuit into a P-FinFET.
Dependencies are inferred from the claim text.