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US 2011/0215827 A1Published application
Method and Apparatus for Testing a Memory Device
AssigneeQUALCOMM Incorporated
InventorsBaker S. Mohammad, Hong S. Kim, Paul D. Bassett
Life of this patent
Estimating the term…
Abstract
In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Claims25
A method of testing a semiconductor device, the method comprising:
- receiving a testing activation signal at a controller coupled to the semiconductor device;
- biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal, wherein the bias is provided by a biasing circuit responsive to the controller;
- and
- performing a test of the semiconductor device to generate testing data while the well is biased.
1 more element
An apparatus comprising:
- a bias circuit configured to provide a bias voltage to a well terminal of at least one transistor of a semiconductor device;
- and
- a controller coupled to the bias circuit, the controller comprising:
- an activation interface configured to receive an activation signal;
- a bias circuit interface configured to send an enable signal to the bias circuit in response to the activation signal;
- and
- a semiconductor device interface configured to send a control signal to the semiconductor device to initiate a test of the semiconductor device, the semiconductor device interface further configured to receive testing data from the semiconductor device corresponding to the test of the semiconductor device.
4 more elements
An apparatus comprising:
- means for receiving a testing activation signal at a controller coupled to a memory device of a semiconductor device;
- means for biasing a well of at least one transistor of the memory device in response to the received testing activation signal, wherein the bias is provided by a biasing circuit responsive to the controller;
- and
- means for performing a test of the memory device to generate testing data while the well is biased.
1 more element
Dependencies are inferred from the claim text.