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US 2011/0215787 A1Published application
Boosting circuit and rfid tag including boosting circuit
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYutaka Shionoiri, Junpei Sugao
Life of this patent
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Abstract
One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.
Claims23
A boosting circuit comprising n stages of unit boosting circuits electrically connected to each other in series (n is a natural number and an even number), each unit boosting circuit comprising:
- a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
- a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
- a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode;
- a fourth transistor comprising a fourth gate electrode, a fourth source electrode, and a fourth drain electrode;
- a first capacitor;
- a second capacitor;
- and
- an analog switch comprising a first terminal, a second terminal, a third terminal, and a fourth terminal,
- wherein the first gate electrode, one of the first source electrode and the first drain electrode, one of the second source electrode and the second drain electrode, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another,
- wherein the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and the fourth gate electrode are electrically connected to one another,
- wherein the other of the second source electrode and the second drain electrode, the other electrode of the first capacitor, and one of the third source electrode and the third drain electrode are electrically connected to one another,
- wherein the other of the third source electrode and the third drain electrode and a low-potential power supply are electrically connected to each other,
- wherein the other of the fourth source electrode and the fourth drain electrode, one electrode of the second capacitor, and the first terminal of the analog switch are electrically connected to one another,
- wherein the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit is configured to be input an input signal,
- wherein the third gate electrode and the other electrode of the second capacitor in a (2M−1)th stage unit boosting circuit is configured to be input a clock signal (M is a natural number which satisfies 1≦M≦n/2)),
- wherein the third gate electrode and the other electrode of the second capacitor in the 2M-th stage unit boosting circuit is configured to be input an inverted clock signal,
- wherein the second terminal of the analog switch is configured to be input the clock signal and the third terminal of the analog switch is configured to be input the inverted clock signal in a (2M−1)th stage unit boosting circuit,
- wherein the second terminal of the analog switch is configured to be input the inverted clock signal and the third terminal of the analog switch is configured to be input the clock signal in the 2M-th stage unit boosting circuit,
- wherein the other of the fourth source electrode and the fourth drain electrode in an n-th stage unit boosting circuit is configured to output a signal obtained by boosting the input signal,
- wherein a potential of the low-potential power supply is lower than a potential of the input signal, and
- wherein the fourth terminal of the analog switch in a (K−1)th stage unit boosting circuit (K is a natural which satisfies 2≦K≦n) is electrically connected to the one of the first source electrode and the first drain electrode in a K-th stage unit boosting circuit.
18 more elements
A boosting circuit comprising:
- a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
- a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
- a first capacitor;
- and
- a second capacitor,
- wherein the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another,
- wherein the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another,
- wherein the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other,
- wherein the one of the first source electrode and the first drain electrode is configured to be input an input signal,
- wherein the other electrode of the second capacitor is configured to be input a clock signal, and
- wherein the other of the first source electrode and the first drain electrode is configured to output a signal obtained by boosting the input signal.
8 more elements
A boosting circuit comprising n stages of unit boosting circuits electrically connected to each other in series (n is a natural number and an even number), each unit boosting circuit comprising:
- a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
- a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
- a first capacitor;
- and
- a second capacitor,
- wherein the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another,
- wherein the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another,
- wherein the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other,
- wherein the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit is configured to be input an input signal,
- wherein the other electrode of the second capacitor in a (2M−1)th stage unit boosting circuit is configured to be input a clock signal (M is a natural number which satisfies 1≦M≦n/2),
- wherein the other electrode of the second capacitor in a 2M-th stage unit boosting circuit is configured to be input an inverted clock signal, and
- wherein the other of the first source electrode and the first drain electrode in an n-th stage unit boosting circuit is configured to output a signal obtained by boosting the input signal.
9 more elements
A boosting circuit comprising n stages of unit boosting circuits electrically connected to each other in series (n is a natural number greater than one), each unit boosting circuit comprising:
- a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
- a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
- a first capacitor;
- and
- a second capacitor,
- wherein the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another,
- wherein the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another,
- wherein the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other,
- wherein the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit is configured to be input an input signal,
- wherein the other of the first source electrode and the first drain electrode in an n-th stage unit boosting circuit is configured to output a signal obtained by boosting the input signal,
- wherein the other electrode of the second capacitor in the n-th stage unit boosting circuit is configured to be input an inverted clock signal,
- wherein, for all values of M, where M is a natural number which satisfies 1≦M≦(n−1):
- when n is an even number and M is an odd number, or n is an odd number and M is an even number, the other electrode of the second capacitor in a M-th stage unit boosting circuit is configured to be input a clock signal, and
- when n is an even number and Al is an even number, or n is an odd number and M is an odd number, the other electrode of the second capacitor in the M-th stage unit boosting circuit is configured to be input an inverted clock signal.
11 more elements
A boosting circuit comprising n stages of unit boosting circuits electrically connected to each other in series (n is a natural number greater than one), each unit boosting circuit comprising:
- a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
- a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
- a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode;
- a fourth transistor comprising a fourth gate electrode, a fourth source electrode, and a fourth drain electrode;
- a first capacitor;
- a second capacitor;
- and
- an analog switch comprising a first terminal, a second terminal, a third terminal, and a fourth terminal,
- wherein the first gate electrode, one of the first source electrode and the first drain electrode, one of the second source electrode and the second drain electrode, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another,
- wherein the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and the fourth gate electrode are electrically connected to one another,
- wherein the other of the second source electrode and the second drain electrode, the other electrode of the first capacitor, and one of the third source electrode and the third drain electrode are electrically connected to one another,
- wherein the other of the third source electrode and the third drain electrode and a low-potential power supply are electrically connected to each other,
- wherein the other of the fourth source electrode and the fourth drain electrode, one electrode of the second capacitor, and the first terminal of the analog switch are electrically connected to one another,
- wherein the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit is configured to be input an input signal,
- wherein a potential of the low-potential power supply is lower than a potential of the input signal,
- wherein the fourth terminal of the analog switch in a (K−1)th stage unit boosting circuit (K is a natural number which satisfies 2≦K≦n) is electrically connected to the one of the first source electrode and the first drain electrode in a K-th stage unit boosting circuit,
- wherein the other of the fourth source electrode and the fourth drain electrode in an n-th stage unit boosting circuit is configured to output a signal obtained by boosting the input signal,
- wherein the other electrode of the second capacitor in the n-th stage unit boosting circuit is configured to be input an inverted clock signal, and
- wherein, for all values of M, where M is a natural number which satisfies 1≦M≦(n−1):
- when n is an even number and M is an odd number, or n is an odd number and M is all even number, in a M-th stage:
- the third gate electrode and the other electrode of the second capacitor is configured to be input a clock signal;
- the second terminal of the analog switch is configured to be input a clock signal;
- and
- the third terminal of the analog switch is configured to be input an inverted clock signal, and
- when n is all even number and Al is an even number, or n is an odd number and M is an odd number, in the M-th stage:
- the third gate electrode and the other electrode of the second capacitor is configured to be input an inverted clock signal;
- the second terminal of the analog switch is configured to be input an inverted clock signal;
- and
- the third terminal of the analog switch is configured to be input a clock signal.
26 more elements
Dependencies are inferred from the claim text.