Integrated circuit structure and method for manufacturing the same
AssigneeUnited Microelectronics Corp.
InventorYan-Hsiu LIU
Life of this patent
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Abstract
A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Nest, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.
Claims20
A method for manufacturing an integrated circuit structure, comprising:
- forming a dielectric layer on a substrate having a transistor region and a diode region;
- forming a contact hole and an opening in the dielectric layer simultaneously, the contact hole exposing a portion of the substrate at the transistor region, the opening exposing a portion of the substrate at the diode region, and a size of the opening being larger than that of the contact hole;
- forming a first metal layer on the dielectric layer and filling the contact hole and the opening;
- removing a portion of the first metal layer to form a contact plug above the transistor region and simultaneously form a metal spacer on a sidewall of the opening;
- performing an ion implantation process by using the metal spacer as a mask, so as to form a lightly doped region in the substrate at a bottom of the opening;
- and
- forming a contact metal layer on the lightly doped region.
An integrated circuit structure, comprising:
- a substrate having a transistor region and a diode region;
- a dielectric layer disposed on a substrate, the dielectric layer defining a contact hole and an opening therein, the contact hole exposing a portion of the substrate at the transistor region, the opening exposing a portion of the substrate at the diode region, and a size of the opening being larger than that of the contact hole;
- a contact plug disposed in the contact hole of the dielectric layer;
- a metal spacer disposed on a sidewall of the opening of the dielectric layer;
- a lightly doped region disposed in the substrate at a bottom of the opening that is not covered by the metal spacer and an edge of the lightly doped region is aligned with an edge of the metal spacer;
- and
- a contact metal layer disposed on the lightly doped region.
Dependencies are inferred from the claim text.