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US 2011/0215470 A1Published application
Dummy Wafers in 3DIC Package Assemblies
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Fa Chen, Chia-Yen Lee
Life of this patent
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Abstract
A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.
Claims20
A package structure comprising:
- a first die;
- a second die over and bonded to the first die, wherein the second die has a size smaller than a size of the first die;
- and
- a dummy chip over and bonded to the first die, wherein the dummy chip comprises a portion encircling the second die, and wherein the dummy chip comprises a material selected from the group consisting essentially of silicon and a metal.
1 more element
A package structure comprising:
- an interposer die substantially free from integrated circuit devices formed therein;
- a first die over and bonded to the interposer die, wherein the first die has a horizontal size smaller than a horizontal size of the interposer die;
- and
- a dummy chip substantially free from integrated circuit devices over and bonded to the interposer die, wherein the dummy chip comprises a portion encircling the first die, and wherein the dummy chip comprises a material selected from the group consisting essentially of silicon and a metal.
1 more element
Dependencies are inferred from the claim text.