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US 2011/0215465 A1Published application
Multi-chip integrated circuit
AssigneeXilinx, Inc.
InventorsArifur Rahman, Venkatesan Murali
Life of this patent
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Abstract
An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.
Claims18
An integrated circuit (“IC”), comprising:
- a first IC chip having a first on-chip interconnect structure, the first IC chip being mounted on a reconstructed wafer base;
- a second IC chip having a second on-chip interconnect structure, the second IC chip being mounted on the reconstructed wafer base;
- wherein the first IC die has an oxide layer on an edge, the second IC die has an oxide layer on an edge, and the oxide layers on the edges of the first IC die and the second IC die are in contact with one another and bonded together;
- and
- a chip-to-chip interconnect structure disposed on the first IC chip and on the second IC chip;
- wherein the chip-to-chip interconnect structure electrically couples the first on-chip interconnect structure to the second on-chip interconnect structure.
3 more elements
A method of fabricating one or more composite integrated circuits (“ICs”), the method comprising:
- producing IC dice, each IC die having an on-chip interconnect structure;
- polishing edges of the IC dice;
- depositing an oxide layer to coat the edges of the IC dice to form edge oxide layers on the edges;
- activating the edge oxide layers;
- arranging the IC dice on an edge-bonding carrier in one or more composite IC patterns;
- forcing the IC dice on the edge-bonding carrier together, wherein the oxide layers contact and bond with one another on the edges of adjacent ones of the IC dice
- forming a reconstructed wafer base on the IC dice to form a reconstructed;
- wafer;
- fabricating a chip-to-chip interconnect structure on the reconstructed wafer to electrically couple the on-chip interconnect structures;
- and
- singulating one or more composite ICs from the reconstructed wafer.
8 more elements
(canceled)
Dependencies are inferred from the claim text.