Dummy TSV to Improve Process Uniformity and Heat Dissipation
AssigneeATI Technologies ULC
InventorChangyok Park
Life of this patent
Estimating the term…
Abstract
In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.
Claims20
A method of forming at least a first integrated circuit for use in assembling a multi-chip stack, the method comprising:
- patterning and etching a first plurality of through-silicon via openings in at least a first integrated circuit comprising:
- at least a first through-silicon via opening that extends through the entirety of the first integrated circuit without penetrating any active circuit region formed in the first integrated circuit, and
- at least a second through-silicon via opening that extends down to, but not through, any active circuit regions formed in the first integrated circuit;
- and
- forming one or more conductive layers in the first plurality of through-silicon via openings to form a first plurality of through-silicon via structures in the first integrated circuit for thermally conducting heat.
A method of fabricating an integrated circuit having a plurality of device layers, comprising:
- providing a first wafer substrate comprising a plurality of chip areas, each chip area comprising one or more active circuit regions formed on a first side of the first wafer substrate;
- and
- forming first and second conductive through-silicon via structures in each of the plurality of chip areas, comprising a first conductive through-silicon via structure which extends through the first wafer substrate without penetrating any of the one or more active circuit regions, and a second conductive through-silicon via structure which extends partially through the first wafer substrate without penetrating any active circuit region in the first wafer substrate.
An integrated circuit having a plurality of device layers, comprising:
- a first substrate layer comprising a first side, a second side on which a first active circuit area is formed, a first set of thermally or electrically conductive through-silicon via structures which extend through the first substrate layer without penetrating the first active circuit area, and a second set of thermally conductive through-silicon via structures which extend only partially through the first substrate layer for conducting heat from the first active circuit area;
- a first dielectric layer formed over the first side of the first substrate layer comprising a third set of thermally or electrically conductive through-silicon via structures which extend through the first dielectric layer and align with the first set of thermally or electrically conductive through-silicon via structures and the second set of thermally conductive through-silicon via structures;
- a second substrate layer formed over the first dielectric layer, the second substrate layer comprising a first side, a second side on which a second active circuit area is formed, a fourth set of thermally or electrically conductive through-silicon via structures which extend through the second substrate layer for alignment with the third set of thermally or electrically conductive through-silicon via structures in the first dielectric layer, and a fifth set of thermally conductive through-silicon via structures which extend only partially through the second substrate layer for conducting heat from the second active circuit area;
- and
- a heat sink formed over the second substrate layer that is in thermal contact with the first, second, third, fourth and fifth sets of conductive through-silicon via structures.
Dependencies are inferred from the claim text.