Stacked Semiconductor Packages
AssigneeSamsung Electronics Co., Ltd.
InventorsChoong-Bin Yim, Seung-Kon Mok, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim
Life of this patent
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Abstract
Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.
Claims21
A stacked semiconductor package, comprising:
- a first semiconductor package including a first printed circuit board and at least one first semiconductor device mounted on the first printed circuit board;
- a second semiconductor package stacked on the first semiconductor package, the second semiconductor package including a second printed circuit board and at least one second semiconductor device mounted on the second printed circuit board;
- and
- a first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the at least one first semiconductor device.
A semiconductor package, comprising:
- a lower package including a lower substrate, at least one first semiconductor chip mounted on the lower substrate, and a plurality of first through electrodes electrically connected to the lower substrate through the at least one first semiconductor chip;
- an upper substrate attached to the lower package;
- a second semiconductor chip mounted on the upper substrate;
- and
- a plurality of conductive patterns between the lower package and the upper substrate and connected to the plurality of first through electrodes, wherein all of the plurality of conductive patterns are arranged on the at least one first semiconductor chip.
A semiconductor package, comprising:
- a lower package including a lower substrate, at least one first semiconductor chip adjacent to the lower substrate, a plurality of through electrodes penetrating the at least one first semiconductor chip, and an interposer adjacent to the first semiconductor chip;
- an upper substrate attached to the lower package;
- a second semiconductor chip mounted on the upper substrate;
- and
- a plurality of conductive patterns between the lower package and the upper substrate,
- wherein the interposer includes a plurality of front pads on a first surface, and a plurality of back pads formed on a second surface facing the first surface and electrically connected to the front pads.
21-39. (canceled)
Dependencies are inferred from the claim text.