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US 2011/0215446 A1Published application
Chip package and method for fabricating the same
AssigneeMegica Corporation
InventorMou-Shiung Lin
Life of this patent
Estimating the term…
Abstract
A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.
Claims21
1-20. (canceled)
A chip package comprising:
- a circuit substrate comprising a glass substrate, a first metal interconnect at a top side of said glass substrate, and a second metal interconnect at a bottom side of said glass substrate, wherein said first metal interconnect is connected to said second metal interconnect;
- a semiconductor chip over said top side of circuit substrate, wherein said semiconductor chip comprises a dielectric layer, a first metal layer, a second metal layer and a third metal layer connecting said first metal layer to said second metal layer, wherein said third metal layer is connected to said first metal layer through an opening in said dielectric layer, wherein said third metal layer is connected to said second metal layer not through any opening in said dielectric layer, wherein said first and second metal layers comprise electroplated copper, and said third metal layer comprises aluminum, wherein said first metal layer is connected to said first metal interconnect through, in sequence, said third metal layer and said second metal layer;
- and
- a solder under said second metal interconnect.
1 more element
A chip package comprising:
- a circuit substrate comprising a glass substrate, a first metal interconnect at a top side of said glass substrate, and a second metal interconnect at a bottom side of said glass substrate, wherein said first metal interconnect is connected to said second metal interconnect;
- a semiconductor chip over said top side of circuit substrate, wherein said semiconductor chip comprises a passivation layer, a first metal layer and a second metal layer connected to said first metal layer through an opening in said passivation layer, wherein said passivation layer comprises a nitride, wherein said first and second metal layers comprise electroplated copper, wherein said first metal layer is connected to said first metal interconnect through said second metal layer;
- and
- a solder under said second metal interconnect.
1 more element
Dependencies are inferred from the claim text.