Package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Woo PARK, Hwan-Sik Lim, Eunchul Ahn
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Abstract
A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.
Claims30
A package substrate comprising:
- a substrate mounted with a semiconductor chip including a plurality of sides defining an outer peripheral;
- and
- a passivation layer disposed on the substrate and having a first opening portion to be connected electrically to the semiconductor chip,
- wherein the first opening portion extends beyond at least one side among the plurality of sides of the semiconductor chip.
A semiconductor package comprising:
- a semiconductor chip including a plurality of sides defining an outer peripheral;
- a package substrate providing a region mounted with the semiconductor chip;
- and
- a molding layer configured to mold the semiconductor chip,
- wherein the package substrate includes a first opening portion to be connected electrically to the semiconductor chip and that extends beyond at least one side among the plurality of sides of the semiconductor chip.
A semiconductor package comprising:
- a semiconductor chip including a top surface with an electrical connection terminal and a support terminal disposed thereon and a bottom surface opposite to the top surface;
- a substrate mounted with a semiconductor chip including a plurality of sides defining an outer peripheral;
- a passivation layer disposed on the substrate and having a first opening portion to be connected electrically to the semiconductor chip,
- wherein the first opening portion extends beyond at least one side among the plurality of sides of the semiconductor chip;
- and
- a molding layer molding the semiconductor chip and filling a gap between the semiconductor chip and the package substrate,
- wherein the package substrate further includes a second opening portion connected to the support terminal, and
- wherein the semiconductor chip is disposed such that the top surface faces the package substrate, the electrical connection terminal is electrically connected through the first opening portion to the package substrate, and the support terminal is connected through the second opening portion to the package substrate to mechanically support the semiconductor chip on the package substrate.
22-26. (canceled)
A substrate including a semiconductor chip having a plurality of sides defining an outer periphery thereof, the substrate comprising:
- a passivation layer disposed thereon, the passivation layer including:
- an edge connection region formed within boundary edges of the passivation layer to have a perimeter equal to the outer periphery of the semiconductor chip;
- and
- at least one center portion formed therein along a width of the passivation layer to extend path both opposing sides of the edge connection region.
A package substrate comprising:
- a passivation layer including an open region extending therethrough;
- at least one dam having a predetermined height and being formed on the passivation layer;
- and
- a chip disposed on the at least one dam to define a gap between the chip and the passivation layer.
(canceled)
Dependencies are inferred from the claim text.