Semiconductor integrated circuit device with reduced leakage current

A semiconductor device comprising:

• a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other;
• a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells;
• a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells;
• and
• a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line, the power voltage control circuit having a third N-channel MOS transistor,
• wherein, in a drain region of the first N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus,
• wherein, in a drain region of the second N-channel MOS transistor, a contact region thereof includes arsenic and an extension region thereof includes phosphorus, and
• wherein, in a drain region of the third N-channel MOS transistor, each of a contact region and an extension region thereof includes arsenic.