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AssigneesNational University Corporation Tohoku University, Tokyo Electron Limited, Ube Industries, Ltd., Ube-Nitto Kasei Co., Ltd.
InventorsTadahiro Ohmi, Takaaki Matsuoka, Atsutoshi Inokuchi, Kohei Watanuki, Tadashi Koike, Tatsuhiko Adachi
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In manufacturing processes of a semiconductor device including a shallow trench element isolation region and an interlayer insulating film of a multilayer structure, it is necessary to repeatedly use CMP, but since the CMP itself is costly, the repeated use of the CMP is a cause to increase the manufacturing cost. As an insulating film for use in a shallow trench (ST) element isolation region and/or a lowermost-layer interlayer insulating film, use is made of an insulating coating film that can be coated by spin coating. The insulating coating film has a composition expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x(where n=1 to 3 and 0≦x≦1.0) and a film with a different relative permittivity k is formed by selecting heat treatment conditions. The STI element isolation region can be formed by modifying the insulating coating film completely to a SiO2 film, while the interlayer insulating film with a small relative permittivity k can be formed by converting it to a state not completely modified.
A semiconductor device comprising an element isolation region, wherein:
A method of manufacturing a semiconductor device comprising an element isolation region, said method comprising:
A semiconductor device comprising an interlayer insulating film of a multilayer structure, wherein a lowermost layer of said interlayer insulating film includes a coating film expressed by a general formula of ((CH3)nSiO2-n/2)x( SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
A semiconductor device manufacturing method comprising a step of forming a plurality of semiconductor elements on a semiconductor substrate, a step of forming a first interlayer insulating film on said semiconductor substrate, a step of forming an electrode layer that penetrates said first interlayer insulating film so as to be electrically connected to at least one of a plurality of regions forming each of said semiconductor elements, and a step of forming a first wiring layer on said first interlayer insulating film so as to be electrically connected to said electrode layer, wherein said step of forming a first interlayer insulating film comprises a step of coating a first coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x( SiO2)1-x (where n=1 to 3 and 0≦x≦1.0) and a step of forming a first insulating film having a predetermined permittivity by heat-treating said first coating film at a predetermined temperature.
A method of manufacturing a semiconductor device comprising an element isolation region and an interlayer insulating film, wherein mutually different heat treatments are applied to the same composition, thereby forming said element isolation region and said interlayer insulating film having mutually different permittivities.
A semiconductor device comprising a semiconductor substrate, a semiconductor element having a plurality of regions and formed on said semiconductor substrate, a first interlayer insulating film formed on said semiconductor substrate, an electrode layer penetrating said first interlayer insulating film so as to be electrically connected to at least one of said plurality of regions, and a first wiring layer provided on said first interlayer insulating film so as to be electrically connected to said electrode layer, wherein said first interlayer insulating film includes a first coating film comprising one kind or two or more kinds of compositions expressed by a general formula of ((CH3)nSiO2-n/2)x( SiO2)1-x (where n=1 to 3 and 0≦x≦1.0).
Dependencies are inferred from the claim text.