Structure and Method for Forming Planar Gate Field Effect Transistor with Low Resistance Channel Region

A vertically-conducting planar-gate field effect transistor comprising:

• a silicon region of a first conductivity type;
• a silicon-germanium layer extending over the silicon region;
• gate electrode laterally extending over but being insulated from the silicon-germanium layer;
• a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region;
• and
• source region of the first conductivity type extending in the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

A method of forming a vertically-conducting planar-gate field effect transistor comprising:

• forming a silicon-germanium layer over a silicon region of a first conductivity type;
• forming a gate electrode laterally extending over but insulated from the silicon-germanium layer;
• forming a body region of a second conductivity type extending in the silicon-germanium layer and the silicon region;
• and
• forming a source region of the first conductivity type extending at least into the silicon-germanium layer, the gate electrode laterally overlapping both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.