Thyristor based memory cells, devices and systems including the same and methods for forming the same

A semiconductor device comprising:

• at least one conductive strap;
• a plurality of memory cells disposed on the at least one conductive strap, each of the plurality of memory cells comprising:
• a thyristor comprising a plurality of alternately doped, vertically superposed semiconductor regions;
• and
• a control gate associated with the thyristor;
• and
• a data line electrically coupled with at least a portion of the plurality of memory cells.

A memory array, comprising:

• an array of memory cells comprising:
• a plurality of thyristors substantially aligned in a plurality of rows in a first direction and in a plurality of columns in a second direction perpendicular to the first direction, each of the plurality of thyristors comprising a plurality of vertically superposed, alternately doped semiconductor regions;
• and
• at least one control gate electrically coupled with one of the plurality of vertically superposed, alternately doped semiconductor regions of each thyristor of the plurality of thyristors in at least one of the plurality of columns;
• and
• a plurality of conductive straps, each electrically coupled with each thyristor of the plurality of thyristors in at least one of the plurality of rows.

A method of forming a semiconductor device, comprising:

• forming a semiconductor structure comprising amorphous silicon overlying an electrically insulative material, a conductive material overlying the amorphous silicon, a doped material overlying the conductive material and a doped crystalline silicon overlying the doped material;
• removing portions of each of the doped crystalline silicon, the doped material, the conductive material and the amorphous silicon to form a plurality of channels exposing the electrically insulative material;
• removing portions of the doped crystalline silicon and the doped material to form a plurality of pillars, each pillar of the plurality of pillars including a first doped region and a second doped region oppositely doped with respect to the first doped region;
• forming at least one control gate on at least one surface of each pillar of the plurality of pillars;
• exposing the plurality of pillars to a first dopant to form a third doped region, oppositely doped with respect to the second doped region;
• exposing the plurality of pillars to a second dopant to form a fourth doped region.

A system comprising:

• at least memory access device;
• and
• at least one semiconductor device operably coupled to the at least one memory access device and comprising:
• at least one conductive strap;
• and
• a plurality of memory cells disposed on the at least one conductive strap, each of the plurality of memory cells comprising:
• a thyristor;
• and
• a control gate associated with the thyristor;
• and
• a data line electrically coupled with at least a portion of the plurality of memory cells.