Polysilicon resistor and e-fuse for integration with metal gate and high-k dielectric

A resistive polycrystalline semiconductor device of a microelectronic element, comprising:

• a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, and a polycrystalline semiconductor region overlying the metal gate layer, the polycrystalline semiconductor region including a first polycrystalline semiconductor region adjacent the metal gate layer, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region, the first polycrystalline semiconductor region having a first predominant dopant type being either p or n, and the second polycrystalline semiconductor region having a second predominant dopant type being either p or n and being opposite the first predominant dopant type;
• and
• first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance.

A method of making an electrical fuse element of a microelectronic element, comprising:

• (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region, the first polycrystalline semiconductor region having a first predominant dopant type being either p or n, and the second polycrystalline semiconductor region having a second predominant dopant type being either p or n and being opposite from the first predominant dopant type, and a silicide region extending over at least a portion of the second polycrystalline semiconductor region;
• and
• (b) forming first and second spaced-apart contacts in conductive communication with the silicide region, wherein at least a portion of the silicide region extends continuously between the first and second contacts and is electrically connected with each of first and second contacts.

An electrical fuse element of a microelectronic element, comprising:

• a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, and a polycrystalline semiconductor region overlying the metal gate layer, the polycrystalline semiconductor region including a first polycrystalline semiconductor region adjacent the metal gate layer, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region, the first polycrystalline semiconductor region having a first predominant dopant type being either p or n, and the second polycrystalline semiconductor region having a second predominant dopant type being either p or n and being opposite from the first predominant dopant type, the layered stack further including a silicide region overlying the second polycrystalline semiconductor region;
• and
• first and second spaced-apart contacts, wherein at least a portion of the silicide region extends continuously between the first and second contacts and is electrically connected with each of first and second contacts.