Semiconductor device and method for manufacturing semiconductor device

A semiconductor device comprising:

• a first transistor;
• and
• a second transistor over the first transistor,
• wherein the first transistor comprises:
• a first channel formation region;
• a first gate insulating layer over the first channel formation region;
• a first gate electrode over the first gate insulating layer so as to overlap with the first channel formation region;
• and
• a first source electrode and a first drain electrode electrically connected to the first channel formation region,
• wherein the second transistor comprises:
• a second source electrode and a second drain electrode embedded in an insulating layer;
• a second channel formation region over and in contact with the insulating layer, the second source electrode, and the second drain electrode;
• a second gate insulating layer over the second channel formation region;
• and
• a second gate electrode over the second gate insulating layer,
• wherein a difference in height exists between an upper surface of the insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a source electrode and a drain electrode over a substrate;
• forming a first insulating layer so as to cover the source electrode and the drain electrode;
• performing planarization treatment on a surface of the first insulating layer, thereby forming a second insulating layer having a planarized surface;
• forming openings reaching the source electrode and the drain electrode in the second insulating layer, so that a difference in height between the planarized surface of the second insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode is formed;
• forming an oxide semiconductor layer over and in contact with the second insulating layer, the source electrode, and the drain electrode;
• forming a gate insulating layer over the oxide semiconductor layer;
• and
• forming a gate electrode over the gate insulating layer.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a source electrode and a drain electrode over a substrate;
• forming a first insulating layer so as to cover the source electrode and the drain electrode;
• performing planarization treatment on a surface of the first insulating layer, thereby forming a second insulating layer having a planarized surface and exposing the source electrode and the drain electrode;
• thinning the source electrode and the drain electrode so that a difference in height between the planarized surface of the second insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode is formed;
• forming an oxide semiconductor layer over and in contact with the second insulating layer, the source electrode, and the drain electrode;
• forming a gate insulating layer over the oxide semiconductor layer;
• and
• forming a gate electrode over the gate insulating layer.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor comprising a channel formation region, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, overlapping with the channel formation region, and a first source electrode and a first drain electrode electrically connected to the channel formation region;
• forming a first insulating layer over the first transistor;
• forming a second source electrode and a second drain electrode over a surface of the first insulating layer;
• forming a second insulating layer so as to cover the second source electrode and the second drain electrode;
• performing planarization treatment on a surface of the second insulating layer, thereby forming a third insulating layer having a planarized surface;
• forming openings reaching the second source electrode and the second drain electrode in the third insulating layer, so that a difference in height between the planarized surface of the third insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode is formed;
• forming an oxide semiconductor layer over and in contact with the third insulating layer, the second source electrode, and the second drain electrode;
• forming a second gate insulating layer over the oxide semiconductor layer;
• and
• forming a second gate electrode over the second gate insulating layer.

A method for manufacturing a semiconductor device, comprising the steps of:

• forming a first transistor comprising a channel formation region, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, overlapping with the channel formation region, and a first source electrode and a first drain electrode electrically connected to the channel formation region;
• forming a first insulating layer over the first transistor;
• forming a second source electrode and a second drain electrode over a surface of the first insulating layer;
• forming a second insulating layer so as to cover the second source electrode and the second drain electrode;
• performing planarization treatment on a surface of the second insulating layer, thereby forming a third insulating layer having a planarized surface and exposing the second source electrode and the second drain electrode;
• thinning the second source electrode and the second drain electrode so that a difference in height between the planarized surface of the third insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode is formed;
• forming an oxide semiconductor layer over and in contact with the third insulating layer, the second source electrode, and the second drain electrode;
• forming a second gate insulating layer over the oxide semiconductor layer;
• and
• forming a second gate electrode over the second gate insulating layer.