Improved data-processing electronics for use in a positron-emission tomography system
AssigneeUniversity of Washington
InventorsThomas K. Lewellen, Robert S. Miyaoka
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Abstract
Improved processing electronic hardware are disclosed that facilitate the efficient processing of PET system data, while enhancing accuracy and compatibility of PET systems with other analytical methods (e.g., magnetic resonance imaging). Improvements include the use of an application-specific integrated circuit (ASIC) for summing, by row, column, and diagonal, the output signals from an array of photodetectors in the PET system
Claims17
An application specific integrated circuit (ASIC) useful in a positron emission tomography (PET) system to transfer and process analog signals between a two-dimensional array of photodetectors and a digital processing board;
- said array of photodetectors comprising rows and columns of photodetectors arranged in a grid, with each photodetector in the array having a common bias voltage;
- and
- said ASIC being configured to perform the following functions:
- I. sum single-ended analog signals from the array of photodetectors in row, column, and diagonal operations;
- II. provide bandwidth amplification of a bias signal from the common bias voltage, said bias signal being useful as a common timing signal for the photodetectors in the array;
- III. provide bandwidth amplification for single-ended signals from each photodetector in the array;
- IV. produce a total summed signal from the signals from the array;
- V. provide a gain adjustment of up to +/−30% for each photodetector prior to summing the signals;
- VI. provide bias voltage adjustment for each photodetector in the array;
- VII. provide differential signal outputs compatible with analog-to-digital converters on the digital processing board;
- and
- VIII. provide individual addressing of a single photodetector in the array with all other photodetectors excluded.
A data acquisition system for a positron emission tomography scanner having a plurality of detector modules, each detector module having an array of photodetectors associated with corresponding scintillation crystals, the data acquisition system comprising:
- (a) for each detector module, a board set including:
- (i) a detector adaptor board that supplies voltage control to the associated array of photodetectors and receives single-ended analog signals from the associated array of photodetectors, and further comprises means for converting the received single-ended signals to differential pairs;
- and (ii) a digitizing board that receives and digitizes the differential pair signals from the detector adaptor board and produces an event strobe signal in response to the received differential pair signals;
- (b) a master board that receives the event strobe signals from the board sets from each detector module and preliminarily identifies coincident events based on the timing of the received event strobe signals and the location of the detector modules associated with the received event strobe signals;
- (c) a master clock board that provides a master clock signal to the board sets;
- wherein the master board further comprises means for sending an event_OK signal to the detector modules associated with the identified coincident events, and the digitizing boards further comprise means for responding to the event_OK signal by packaging the digitized differential pair signals associated with the event_OK signal with time stamp data and transmitting the packaged data to an image processing apparatus.
A method for reducing the number of data signals between an analog photodetector array and a digital processing board in a positron emission tomography (PET) system, comprising the steps of:
- (a) providing an application specific integrated circuit (ASIC) to transfer and process analog signals between a two-dimensional array of photodetectors and a digital processing board;
- said array of photodetectors comprising a square grid of N by N photodetectors;
- with each photodetector in the array having a common bias voltage;
- said ASIC being configured to perform the following functions:
- I. sum single-ended analog signals from the array of photodetectors in row, column, and diagonal operations in a summing array;
- II. provide bandwidth amplification of a bias signal from the common bias voltage, said bias signal being useful as a common timing signal for the photodetectors in the array;
- III. provide bandwidth amplification for single-ended signals from each photodetector in the array;
- IV. produce a total summed signal from the signals from the array;
- V. provide a gain adjustment of up to +/−30% for each photodetector prior to summing the signals;
- VI. provide bias voltage adjustment for each photodetector in the array;
- VII. provide differential signal outputs compatible with analog-to-digital converters on the digital processing board;
- and
- VIII. provide individual addressing of a single photodetector in the array with all other photodetectors excluded;
- (b) routing up to N2 single-ended analog signals from the array of photodetectors into a summing array in the ASIC for a single time increment;
- (c) summing the plural number of single-ended analog signals in the summing array using row, column, and diagonal operations to produce between 3N and 4N output signals;
- and
- (d) outputting from the ASIC a plural number of differential output analog signals;
- wherein the plural number of single-ended analog signals input into the ASIC is larger than the plural number of differential-output analog signals.
Dependencies are inferred from the claim text.