Semiconductor design support apparatus

A semiconductor design support control method applied to a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment, the semiconductor design support control method comprising:

• a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information;
• a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from a plurality of blocks;
• an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment;
• and
• an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.

A non-transitory computer-readable storage medium storing a semiconductor design support control program for causing a computer to execute a process, the computer constituting a semiconductor design support apparatus that reads circuit description information and generates information required for delay adjustment, the process comprising:

• a logic simulation step of performing logic simulation based on the circuit description information and outputting logic simulation result information;
• a latency information acquiring step of acquiring, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from a plurality of blocks;
• an adjustment latency calculating step of calculating, from the latency information, adjustment latency information required for the delay adjustment;
• and
• an adjustment delay information generating step of generating, from the adjustment latency information, adjustment delay information required for the delay adjustment.