Method for Preparing Re-Architected Designs for Sequential Equivalence Checking
AssigneeIntrinsity, Inc.
InventorMark H. Nodine
Life of this patent
Estimating the term…
Abstract
This disclosure describes a method illustrated in FIG. 7 to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processes 100 a configuration file. Then, the method 105 computes one or more output files. Finally, the method 110 writes the output files.
Claims20
A method for preparing re-architected integrated circuit (IC) designs for sequential equivalence checking the method comprising:
- providing a description of an IC design module that includes a plurality of ports;
- providing a description of an IC reference model that includes a sub-circuit that matches the IC design module and a hierarchy of one or more reference modules, wherein each of said reference modules includes a plurality of internal signals;
- creating a configuration file that includes an instance definition, wherein said instance definition contains a plurality of port definitions, each said port definition contains the name of a port of said IC design module and a reference connection, and said reference connection contains a Boolean combination of a plurality of signals within a plurality of reference modules and the Boolean constants 0 and 1;
- generating a plurality of files based upon said configuration file;
- wherein said plurality of files includes:
- a reference wrapper file that encapsulates the IC reference model and includes a first set of primary inputs and outputs;
- a design wrapper file that encapsulates the IC design module and includes a second set of primary inputs outputs, wherein said second set of primary inputs and outputs is identical to said first set of primary inputs and outputs;
- and
- one or more hierarchical override files for verifying said IC design module against said IC reference model, wherein each of said hierarchical override files modifying an individual module within the hierarchy of one or more reference modules of said IC reference model by adding one or more additional ports to access internal signals within said individual module;
- wherein said reference wrapper file is sequentially equivalent to said design wrapper file in response to said IC design module correctly implementing the sub-circuit of said IC reference model specified by said configuration file, and as modified by said hierarchical override files.
A system for preparing re-architected integrated circuit (IC) designs for sequential equivalence checking, where the IC designs include a description of IC design module that includes a plurality of ports, and a description of an IC reference model that includes a sub-circuit that matches the IC design module and a hierarchy of one or more reference modules, each including a plurality of internal signals, the system comprising:
- a processor;
- a storage device coupled to the processor;
- wherein the processor is configured to execute instructions stored on the storage device to:
- create a configuration file that includes an instance definition, wherein said instance definition contains a plurality of port definitions, each said port definition contains the name of a port of said IC design module and a reference connection, and said reference connection contains a Boolean combination of a plurality of signals within a plurality of reference modules and the Boolean constants 0 and 1;
- generate a plurality of files based upon said configuration file, wherein said plurality of files includes:
- a reference wrapper file that encapsulates the IC reference model and includes a first set of primary inputs and outputs;
- a design wrapper file that encapsulates the IC design module and includes a second set of primary inputs outputs, wherein said second set of primary inputs and outputs is identical to said first set of primary inputs and outputs;
- and
- one or more hierarchical override files for verifying said IC design module against said IC reference model, wherein each of said hierarchical override files modifying an individual module within the hierarchy of one or more reference modules of said IC reference model by adding one or more additional ports to access internal signals within said individual module;
- wherein said reference wrapper file is sequentially equivalent to said design wrapper file in response to said electrical IC design module correctly implementing the sub-circuit of said IC reference model specified by said configuration file, and as modified by said hierarchical override files.
A computer readable storage device including program instructions executable by a computing device to perform a method for preparing re-architected integrated circuit (IC) designs for sequential equivalence checking, where the IC designs include a description of an IC design module that includes a plurality of ports, and a description of an IC reference model that includes a sub-circuit that matches the IC design module and a hierarchy of one or more reference modules, each including a plurality of internal signals, the method comprising:
- creating a configuration file that includes an instance definition, wherein said instance definition contains a plurality of port definitions, each said port definition contains the name of a port of said IC design module and a reference connection, and said reference connection contains a Boolean combination of a plurality of signals within a plurality of reference modules and the Boolean constants 0 and 1;
- generating a plurality of files based upon said configuration file, wherein said plurality of files includes:
- a reference wrapper file that encapsulates the IC reference model and includes a first set of primary inputs and outputs;
- a design wrapper file that encapsulates the IC design module and includes a second set of primary inputs outputs, wherein said second set of primary inputs and outputs is identical to said first set of primary inputs and outputs;
- and
- one or more hierarchical override files for verifying said IC design module against said IC reference model, wherein each of said hierarchical override files modifying an individual module within the hierarchy of one or more reference modules of said IC reference model by adding one or more additional ports to access internal signals within said individual module;
- wherein said reference wrapper file is sequentially equivalent to said design wrapper file in response to said electrical IC design module correctly implementing the sub-circuit of said IC reference model specified by said configuration file, and as modified by said hierarchical override files.
Dependencies are inferred from the claim text.