Data Decoding Method and Apparatus and Receiver and Communication System Applying the Same
AssigneeNEC Corporation
InventorAyumu Yagihashi
Life of this patent
Estimating the term…
Abstract
A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.
Claims10
1-9. (canceled)
A method for decoding data based on information bits and check bits to be referred for performing error correction processing on the information bits, the method comprising the steps of:
- performing processing predetermined for check bits on first check bits by means of a first processor;
- and
- performing, in parallel, processing for decoding by using information bits and first check bits by means of a decoder and processing on second check bits, which are different from the first check bits, by means of the first processor.
A data processor for decoding data based on information bits and check bits to be referred for performing error correction processing on the information bits, the data processor comprising:
- a first processor for performing processing predetermined for check bits;
- a decoder for performing decoding processing by using information bits and check bits;
- and
- a controller for causing the decoder to perform decoding processing by using information bits and check bits and, in parallel, causing the first processor to process the other check bits.
A method for decoding data based on information bits and check bits to be referred for performing error correction processing on the information bits, the method comprising the steps of:
- storing information bits and check bits in a memory apparatus;
- supplying check bits from the memory apparatus to a first processor for performing processing predetermined for check bits;
- in synchronization with the supply of an output of the first processor to the decoder for performing decoding processing based on information bits and check bits, supplying information bits from the memory apparatus to the decoder without the first processor in the middle;
- and
- performing decoding processing by means of the decoder.
15-17. (canceled)
19-21. (canceled)
A system for decoding data comprising information bits and check bits, the system comprising a switch whose input is connected to an output of a memory for storing the information bits and check bits, one of whose outputs is connected to a first path to a decoder via a rate dematch apparatus, another one of whose outputs is connected to a second path to the decoder without passing through the rate dematch apparatus, wherein the switch outputs the check bits to the first path and outputs the information bits to the second path.
Dependencies are inferred from the claim text.