Hierarchical access of test access ports in embedded core integrated circuits

An integrated circuit comprising:

• A. a test data input lead, a test clock lead, a test mode select lead, and a test data out lead;
• B. a first hierarchical core including:
• i. a first test access port having a test data input coupled to the test data input lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and a test data output coupled to the test data out lead, the first test access port including a boundary scan register having a test data input coupled to the test data input lead and a test data output coupled to the test data output lead, the first test access port having a select S output lead, a select SEL1 output lead, and an enable EN1 input lead;
• ii. first core circuitry having first megamodule circuitry and a second test access port, the second test access port having a test data input coupled to the test data input lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and a test data output coupled to the test data out lead, the second test access port including connections to the first megamodule circuitry, a select SEL2 output lead and an enable EN2 input lead;
• and
• iii. a first test linking module having a test data input coupled to the test data input lead, a test data output coupled to the test data output lead, a clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a select SEL1 input coupled to the select SEL1 output lead, an enable E input, an enable EN1 output coupled to the enable E input and coupled to the enable EN1 input lead, a select SEL2 input coupled to the select SEL2 output lead, and an enable EN2 output coupled to the enable EN2 input lead;
• and
• C. a second hierarchical core including:
• i. a third test access port having a test data input coupled to the test data input lead, a test clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, and a test data output coupled to the test data out lead, the third test access port including a boundary scan register having a test data input coupled to the test data input lead and a test data output coupled to the test data output lead, the third test access port having a select SEL3 output lead, and an enable EN3 input lead;
• and
• ii. a second test linking module having a test data input coupled to the test data input lead, a test data output coupled to the test data output lead, a clock input coupled to the test clock lead, a test mode select input coupled to the test mode select lead, a select SEL3 input coupled to the select SEL3 output lead, an enable EN3 output coupled to the enable EN3 input lead, a select S input connected to the select S output lead, and an enable E output connected to the enable E input.