Secured coprocessor comprising an event detection circuit

A system, comprising:

• a processor;
• a bus;
• and
• a coprocessor coupled to the processor via the bus, the coprocessor including:
• a calculation unit configured to execute at least one command;
• and
• a device having:
• an error detection circuit configured to monitor an execution of the command so as to detect an execution error, to place the coprocessor into an error mode at a beginning of the execution of the command, and to lift the error mode at an end of the execution of the command if no execution error has been detected;
• an event detection circuit configured to detect an appearance of at least one particular event;
• and
• a masking circuit coupled to the error detection circuit and to the event detection circuit configured to mask the error mode while the particular event is undetected, and to declare the error mode externally to the coprocessor if the at least one particular event is detected while the coprocessor is in the error mode.

A securization device comprising:

• an error detection circuit configured to monitor execution of a command, to cause a processor coupled to the securization device to go into an error mode by default as soon as execution of the command begins, and to lift the error mode at the end of execution of the command if no error has been detected;
• an event detection circuit coupled to the error detection circuit and configured to detect an occurrence of at least one particular event;
• and
• a masking circuit coupled to the error detection and event detection circuits and configured to declare the error mode from the securization device if the particular event occurs while the processor is in the error mode.