US 2011/0214008 A1Published application

Network system

AssigneeHitachi, Ltd.

InventorsYUKIHISA TAMURA, Masatoshi SHIBASAKI, Mitsuru ASAYAMA, Tsutomu KAWAIZUMI, Kenji OKAMOTO

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Abstract

A network system having duplicate lines of a primary system and a backup system between a transmitter apparatus and a receiver apparatus is provided. Each of the transmitter apparatus and the receiver apparatus includes an arithmetic operator for conducting a BIP-8 arithmetic operation and a CRC arithmetic operation on an input signal and thereby detecting a bit error. The transmitter apparatus transmits data to both lines. The receiver apparatus includes a switcher. When a bit error is detected in received data of the primary system. the switcher switches control of the primary system and the backup system. Hitless protection switching of a VC path is executed,

Claims14

Dependent claims

A network system comprising a first terminal, a second terminal, a first communication control apparatus for communicating with the first terminal, a second communication control apparatus for communicating with the second terminal, and a first network and a second network installed in parallel between the first communication control apparatus and the second communication control apparatus,

the first communication control apparatus comprising:
a first receiving processor for receiving a first SDH signal from the first terminal,
a first arithmetic operator for conducting an error detecting arithmetic operation on a part of the first SDH signal to detect whether an error is included;
and
a packetizing processor for generating packetized data which includes at least a part of result information of the error detecting arithmetic operation, and
the second communication control apparatus comprising:
a depacketizing processor for converting the packetized data supplied from the first network to depacketized data;
a second arithmetic operator for conducting an error detecting arithmetic operation on a part of the depacketized data and a part of depacketized data to be processed by the depacketizing processor next time to detect whether an error is included;
and
a switcher for switching control of a primary system and a backup system on the first network and the second network when an error has been detected by the error detecting arithmetic operation.

7 more elements

the first communication control apparatus comprising:
a first receiving processor for receiving a first SDH signal from the first terminal;
a first BIP-8 arithmetic operator for conducting a BIP-8 arithmetic operation on a part of the first SDH signal;
a first CRC arithmetic operator or conducting a CRC arithmetic operation on a part of the first SDH signal;
and
a packetizing processor for generating packetized data which includes a part of the first SDH signal and at least a part of result information of the CRC arithmetic operation, and
the second communication control apparatus comprising:
a depacketizing processor for converting the packetized data supplied from the first network to depacketized data;
a second BIP-8 arithmetic operator for conducting a BIP-8 arithmetic operation on a part of the depacketized data;
a second CRC arithmetic operator for conducting a CRC arithmetic operation on a part of the depacketized data and a part of depacketized data to be processed by the depacketizing processor next time;
and
a switcher for switching control of a primary system and a backup system on the first network and the second network when an error has been detected by the CRC arithmetic operation.

9 more elements

Dependencies are inferred from the claim text.