Clock control signal generation circuit, clock selector, and data processing device

A clock-control-signal-generation circuit which generates a control signal for clock switching, and which is placed in a clock selector operable to switch between clock signals including a first clock signal based on first and second clock-stop-permission signals and a clock-resume-permission signal, comprising:

• a before-switching clock processing unit, including
• a first high-frequency clock processing subunit which makes active and outputs a first detection signal on detection of a first state of a second clock signal on condition that a switching-trigger signal is active, and
• a first low-frequency clock processing subunit which makes active and outputs a second detection signal on detection of a first state of a third clock signal on condition that the switching-trigger signal is active, and which makes active and outputs a third detection signal on detection of a second state of the third clock signal on condition that the switching-trigger signal is active, and
• an after-switching clock processing unit, including
• a second high-frequency clock processing subunit which makes active and outputs a fourth detection signal on detection of a first state of a fourth clock signal on condition that the first clock-stop-permission signal is active, and which makes active and outputs a fifth detection signal on detection of a second state of the fourth clock signal on condition that the second clock-stop-permission signal is active, and
• a second low-frequency clock processing subunit which makes active and outputs a sixth detection signal on detection of a first state of a fifth clock signal on condition that the first clock-stop-permission signal is active, and which makes active and outputs a seventh detection signal on detection of a second state of the fifth clock signal on condition that the second clock-stop-permission signal is active,
• wherein the before-switching clock processing unit makes active and outputs the first clock-stop-permission signal on condition that one of the first and second detection signals is active,
• the before-switching clock processing unit makes active and outputs the second clock-stop-permission signal on condition that the third detection signal is active, and
• the after-switching clock processing unit makes active and outputs the clock-resume-permission signal on condition that one of the fourth to seventh detection signals is active.