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US 2011/0213993 A1Published application
Data processing apparatus and method for transferring workload between source and destination processing circuitry
AssigneeArm Limited
InventorPeter Richard Greenhalgh
Life of this patent
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Abstract
In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.
Claims32
A data processing apparatus comprising:
- first processing circuitry and second processing circuitry configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time;
- power control circuitry for independently controlling the power supply to the first processing circuitry and the second processing circuitry;
- a workload transfer controller responsive to a transfer stimulus to control a transfer of performance of the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing circuitry being placed in a power saving condition by the power control circuitry, the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry;
- wherein:
- at least the source processing circuitry has a cache;
- the power control circuitry is configured to maintain at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry;
- the data processing apparatus comprises cache snooping circuitry configured during the snooping period to snoop data values in the cache of the source processing circuitry and to retrieve the snooped data values for the destination processing circuitry;
- and
- the power control circuitry is configured to place said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period.
6 more elements
A data processing apparatus comprising:
- first processing means for performing processing and second processing means for performing processing, the first processing means and second processing means being configured to perform a processing workload such that the processing workload is performed by one of the first processing means and the second processing means at a time;
- power control means for independently controlling the power supply to the first processing means and the second processing means;
- workload transfer control means for, in response to a transfer stimulus, controlling a transfer of performance of the processing workload from a source processing means to a destination processing means prior to the source processing means being placed in a power saving condition by the power control means, the source processing means being one of the first and second processing means and the destination processing means being the other of the first and second processing means;
- wherein:
- at least the source processing means has a cache means for storing cached data values;
- the power control means is configured to maintain at least the cache means of the source processing means in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing means;
- the data processing apparatus comprises cache snooping means for snooping data values in the cache means of the source processing means during the snooping period, and retrieving the snooped data values for the destination processing means;
- and
- the power control means is configured to place said at least the cache means of the source processing means in the power saving condition following the end of the snooping period.
6 more elements
A data processing method for an apparatus comprising first processing circuitry and second processing circuitry configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time;
- the method comprising:
- performing the processing workload with a source processing circuitry, the source processing circuitry being one of the first and second processing circuitry and comprising a cache, the other of the first and second processing circuitry being a destination processing circuitry;
- in response to a transfer stimulus, transferring performance of the processing workload from the source processing circuitry to the destination processing circuitry prior to the source processing circuitry being placed in a power saving condition;
- maintaining at least the cache of the source processing circuitry in a powered condition during a snooping period following the start of performance of the transferred processing workload by the destination processing circuitry;
- during the snooping period, snooping data values in the cache of the source processing circuitry and retrieving the snooped data values for the destination processing circuitry;
- and
- placing said at least the cache of the source processing circuitry in the power saving condition following the end of the snooping period.
4 more elements
A data processing apparatus comprising:
- first processing circuitry and second processing circuitry configured to perform a processing workload such that the processing workload is performed by one of the first processing circuitry and the second processing circuitry at a time;
- a workload transfer controller responsive to a transfer stimulus to control a transfer of performance of the processing workload from a source processing circuitry to a destination processing circuitry prior to the source processing circuitry being placed in a power saving condition by the power control circuitry, the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry;
- wherein:
- at least the destination processing circuitry has a cache;
- the destination processing circuitry is configured to invalidate the cache of the destination processing circuitry before the destination processing circuitry starts performing the transferred processing workload;
- the source processing circuitry is configured to continue performing the processing workload while the cache of the destination processing circuitry is being invalidated;
- and
- the workload transfer controller is configured to transfer the performance of the processing workload to the destination processing circuitry after the cache of the destination processing circuitry has been invalidated.
5 more elements
Dependencies are inferred from the claim text.