Processor core communication in multi-core processor
AssigneeEmpire Technology Development LLC
InventorsAndrew WOLFE, Marc Elliot LEVITT
Life of this patent
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Abstract
Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.
Claims20
A multi-core processor, comprising:
- a first set of processor cores of the multi-core processor, wherein each processor core from the first set of processor cores is configured to dynamically receive a first supply voltage and a first clock signal;
- a second set of processor cores of the multi-core processor, wherein each processor core from the second set of processor cores is configured to dynamically receive a second supply voltage and a second clock signal;
- and
- an interface block coupled to the first set of processor cores and also coupled to the second set of processor cores, wherein the interface block is configured to facilitate communication between the first set of processor cores and the second set of processor cores.
A method for managing communications in a multi-core processor that includes a plurality of processor cores having a first set of processor cores and a second set of processor cores, the method comprising:
- idling communications with one or more of the plurality of processor cores in response to a clock frequency change request for the first set of processor cores;
- and
- resuming communications with one or more of the plurality of processor cores after having determined that a first phase lock loop operation associated with the first set of processor cores has acquired a first lock signal and a second phase lock loop operation associated with the second set of processor cores has also acquired a second lock signal.
A computer-readable medium containing a sequence of instructions for managing communications in a multi-core processor that includes a plurality of processor cores having a first set of processor cores and a second set of processor cores, which when executed by a computing device, causes the computing device to:
- issue a first command to idle communications with one or more of the plurality of processor cores in response to a clock frequency change request for the first set of processor cores;
- issue a second command to resume communications with one or more of the plurality of processor cores after having determined that a first phase lock loop operation associated with the first set of processor cores has acquired a first lock signal and a second phase lock loop operation associated with the second set of processor cores has also acquired a second lock signal.
Dependencies are inferred from the claim text.