Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File

An apparatus comprising:

• two register files, each register file configurable with a first read port and a second read port and operable to hold a plurality of entries of a first bit width;
• three execution units, each execution unit configurable to operate on an entry of the first bit width and two of the three execution units configurable to operate as a combined execution unit on an entry of a second bit width, wherein the second bit width has twice as many bits as the first bit width;
• and
• a control unit receiving a first instruction and a second instruction for parallel execution, wherein the control unit in response to the first instruction configures the addressability of the two register files to access one entry from the plurality of entries at one of the two register files to be operated on by one of the three execution units as a first input value, and wherein the control unit in response to the second instruction configures the addressability of the two register files to access two entries, one from a second read port of each of the two register files, and wherein the control unit combines the two entries into a second input value of the second bit width to be operated on by the combined execution unit.

A method comprising:

• receiving a first instruction and a second instruction for parallel execution;
• accessing an entry of a first bit width from one of two register files as a first input value in response to the first instruction;
• accessing two entries in response to the second instruction, one from each of the two register files, wherein each entry of the two entries is of the first bit width, wherein the two entries are combined to form a second input value of a second bit width;
• operating on the first input value by one of three execution units configured for execution in response to the first instruction;
• and
• operating on the second input value by two of the three execution units configured to operate as a combined execution unit for execution in response to the second instruction and in parallel with operating on the first input value.