Methods and apparatus for optimizing concurrency in multiple core systems

A method of routing transactions over an interconnect for an Integrated Circuit between one or more initiator IP cores and one or more target IP cores including one or more multiple channel aggregate target IP cores coupled to the interconnect, comprising:

• routing a first transaction, from a first thread from a first initiator IP core to a first multiple channel aggregate memory target IP core, in which transaction traffic consists of both non-channel-splitting requests and channel-splitting requests, and wherein a first multiple channel aggregate memory target IP core includes two or more memory channels that populate an address space assigned to the first multiple channel aggregate memory target IP core, and the first multiple channel aggregate memory target IP core appears as a single target to the one or more initiator IP cores;
• assigning with tag logic located within the interconnect a first interconnect tag id number to a first transaction and a second interconnect tag id number to a second transaction from a first thread from a first initiator IP core being routed to the first multiple channel aggregate memory target IP core;
• and
• detecting whether a request of the first transaction from the first thread spans over at least a first and second memory channel in the first multiple channel aggregate memory target IP core and applying interlocks via the tag logic within the interconnect, so that in terms of correctness, all of the responses of the first transaction and second transaction are routed back across the interconnect to the first initiator IP core in the expected execution order.

An Integrated Circuit, comprising:

• multiple initiator IP cores;
• multiple target IP cores including memory IP cores;
• an interconnect to communicate transactions between the multiple initiator IP cores and the multiple target IP cores coupled to the interconnect;
• and
• tag logic located within an agent of the interconnect configured to support dynamic mapping of one tag id space to another tag id space as a transaction moves through the interconnect to allow allocation and de-allocation of internal interconnect tag id numbering during the operation of the integrated circuit, where an assigned internal interconnect tag id number is released for use again by the tag logic when a response, from a given target IP core, corresponding to a last outstanding transaction of a series of transactions associated with both 1) a given thread ID and 2) the assigned internal interconnect tag id number issued by the initiator agent is received back by the initiator agent containing the tag logic that assigned the internal interconnect tag id number.