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US 2011/0213948 A1Published application
Efficient Processor Apparatus and Associated Methods
AssigneeAltera Corporation
InventorSteven Perry
Life of this patent
Estimating the term…
Abstract
An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.
Claims26
An apparatus, comprising:
- a processor, the processor comprising:
- a first memory that stores a first set of instructions;
- and
- a second memory that stores a second set of instructions, each instruction in the second set of instructions being longer than the instructions in the first set of instructions,
- wherein an instruction in the first set of instructions is used as a pointer to a corresponding instruction in the second set of instructions.
2 more elements
An integrated circuit (IC), comprising:
- a processor, the processor comprising:
- a first memory that stores a first set of instructions that addresses a second set of instructions;
- and
- a second memory that stores the second set of instructions,
- wherein the second memory contains cycle offsets to allow scheduling of instructions through time.
2 more elements
A method, comprising:
- obtaining a user's program;
- determining whether the user's program contains at least one custom instruction;
- and
- storing in a microcode memory of a processor the at least one custom instruction, depending on whether the user's program contains at least one custom instruction.
1 more element
Dependencies are inferred from the claim text.