Processor, multiprocessor system, and method of detecting illegal memory access
AssigneeKabushiki Kaisha Toshiba
InventorTakashi MIURA
Life of this patent
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Abstract
A processor included in a multiprocessor system including a shared memory, the processor according to an embodiment of the present invention comprises: a storing unit that stores a break occurrence memory area that is address information of the shared memory; and a break generator that causes memory access break when the break occurrence memory area is accessed and puts the processor to a debug state. The break occurrence memory area includes address information of the shared memory in another processor included in the multiprocessor system.
Claims20
A processor included in a multiprocessor system including a shared memory, the processor comprising:
- a storing unit that stores a break occurrence memory area that is address information of the shared memory;
- and
- a break generator that causes memory access break when the break occurrence memory area is accessed and puts the processor to a debug state, wherein
- the break occurrence memory area includes address information of the shared memory in another processor included in the multiprocessor system.
A multiprocessor system comprising:
- a shared memory;
- a first processor that accesses the shared memory;
- and
- a second processor that accesses the shared memory, wherein
- the first processor includes:
- a first storing unit that stores a first break occurrence memory area that is address information of the shared memory;
- and
- a first break generator that causes memory access break when the first break occurrence memory area is accessed and puts the first processor to a debug state,
- the second processor includes:
- a second storing unit that stores a second break occurrence memory area that is address information of the shared memory;
- and
- a second break generator that causes memory access break when the second break occurrence memory area is accessed and puts the second processor to a debug state, and
- the first break occurrence memory area includes address information of the shared memory in the second processor and the second break occurrence memory area includes address information of the shared memory in the first processor.
A method of detecting illegal access to a shared memory in a multiprocessor system including the shared memory, a first processor, and a second processor, the method comprising:
- designating, as a first break occurrence area, address information of the shared memory accessed by the second processor;
- monitoring access to the shared memory by the first processor;
- and
- putting the first processor to a debug state and causing memory access break when it is monitored that the first processor accesses the designated first break occurrence memory area.
Dependencies are inferred from the claim text.