Phosphorus Activated NMOS Using SiC Process

A method of forming a transistor, comprising:

• forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate under the gate structure;
• etching portions of the substrate on opposing sides of the channel region;
• forming silicon carbon material within the etched portions of the substrate;
• and
• forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant.

A method of forming a transistor comprising:

• forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
• etching portions of the substrate on opposing sides of the channel region;
• forming silicon carbon material within the etched portions of the substrate;
• forming sidewall spacers adjacent to the gate structure;
• forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
• etching away the sidewall spacers;
• forming offset spacers adjacent to the gate structure;
• and
• forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.

A method of forming a transistor comprising:

• forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
• forming sidewall spacers adjacent to the gate structure;
• forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
• etching the sidewall spacers and portions of the source and drain regions within the substrate;
• forming silicon carbon material within etched portions of the substrate;
• forming offset spacers adjacent to the gate structure;
• and
• forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.

A method of forming a transistor comprising:

• forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
• forming sidewall spacers adjacent to the gate structure;
• forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
• etching away the sidewall spacers;
• forming offset spacers adjacent to the gate structure;
• forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers;
• etching the portions of the source and drain regions and extension regions within the substrate;
• and
• forming silicon carbon material within etched portions of the substrate.