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US 2011/0212552 A1Published application
Device manufacturing method
AssigneeNational University Corporation Tohoku University
InventorsSHIGETOSHI SUGAWA, AKINOBU TERAMOTO
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Abstract
There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section.
Claims6
A device manufacturing method, comprising:
- forming the plurality of electronic devices on a wafer;
- forming a plurality of circuits under test on the wafer;
- measuring electric characteristics of the plurality of circuits under test;
- and
- judging whether the respective electronic devices are good or defective, based on positions at which the plurality of circuits under test are provided and the electric characteristics of the respective circuits under test.
2 more elements
Dependencies are inferred from the claim text.