US 2011/0211660 A1Published application

Multi -channel sequential viterbi decoder

AssigneeTopcon Positioning Systems, Inc.

InventorsTimur G. Kelin, Dmitry D. Murzinov, Dmitry A. Pyatkov

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Abstract

A multi-channel sequential Viterbi decoder includes: an input data buffer, a “Read Single Data Word from Input Data Buffer” signal driver, a processing unit selector, a decoder channel parameters registers unit, a processing unit for the “Reset Path Metrics” command, a processing unit for the “Set Path Metric Value for the Given Path Number” command, a processing unit for the “Get Single Bit from the Path with Given Number” command, a processing unit for the “Process Input Samples” command, a decoding paths and path metrics RAM, a unit for generating current decoder channel base address for the decoding paths and path metrics RAM, a unit for generating cell address for the decoding path and path metric RAM, and a data buffers unit for decoder channels output.

Claims20

Dependent claims

A multi-channel sequential Viterbi decoder comprising:

an input data buffer;
a signal driver for reading a single data word from the input data buffer;
a processing unit selector;
a decoder channels parameters registers unit;
a processing unit for resetting path metrics;
a processing unit for setting a path metric value based on a path number;
a processing unit for getting a single bit from the path with assigned number;
a processing unit for processing input samples;
a decoding paths and path metrics random access memory (RAM);
a unit for generating current decoder channel base address for the decoding paths and the path metrics RAM;
a unit for generating cell address for the decoding path and the path metric RAM;
and
a data buffers unit for decoder channels output, wherein:
inputs and outputs of the processing units are connected by first and second buses;
a first input of the unit for generating cell address for the decoding path and path metric RAM is connected to the second bus;
a second and a third inputs of the unit for generating cell address are connected to first and second outputs of the unit for generating current decoder channel base address for the decoding paths and the path metrics RAM;
a first input of the unit for generating current decoder channel base address for the decoding paths and the path metrics RAM is connected to a first input of the decoder channel parameter registers unit and to a first output of the input data buffer;
a second output of the input data buffer is connected to a first input of the processing unit selector;
a second input of the processing unit selector is connected to the second input of the input buffer and to an output of the signal driver;
a first input of the signal driver is connected to a third output of the input buffer;
a fourth and a fifth outputs of the processing unit selector are connected to a first and a second inputs of the processing unit for setting the path metric value;
and
a sixth output of the input buffer is connected to a first input of the processing unit for processing input samples.

20 more elements

A decoder for generating current decoder channel base address for a decoding paths and path metrics RAM, the decoder comprising:

a selector,
a decoding paths and path metrics RAM free area base address register;
a decoding paths and path metrics RAM workspace area base addresses register file, wherein a number of registers in register file equals to a number of decoder channels;
and
a multiplexer, wherein:
at least one input of the unit for generating current decoder channel base address is connected to one input of the selector and to one input of the decoding paths and path metrics RAM free area base address register;
at least one input of the unit for generating current decoder channel base address is connected to another input of the selector and to one input of the multiplexor;
other inputs of the multiplexor are connected to outputs of registers of the decoding paths and path metrics RAM base addresses register file;
outputs of the selector are connected to the registers inputs of the decoding paths and path metrics RAM workspace area base addresses register file;
other inputs of the decoding paths and path metrics RAM workspace area base addresses register file are connected to an output of the decoding paths and path metrics RAM free workspace area base address register;
the decoding paths and path metrics RAM free workspace area base address register is connected to an output of the unit for generating current decoder channel base address for the decoding paths and path metrics RAM;
and
an output of the multiplexor is connected to an output of the unit for generating current decoder channel base address for the decoding paths and path metrics RAM and is connected to a second input of the decoding paths and path metrics RAM free area base address register.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/059,244Filed 19 Apr 2010
Priority: RU 20100700527 Feb 2010
Published: 1 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H04L 1/0054
Arrangements at the receiver end: maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
H03M 13/3738
Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35: with judging correct…
H03M 13/41
Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes: using the Viterbi algorithm or Viterbi processors
H03M 13/413
Using the Viterbi algorithm or Viterbi processors: tail biting Viterbi decoding