Semiconductor memory device
OwnerSeung-Lo KIMinventor
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device having an open bit line structure includes a normal memory cell block, a reference memory cell block, and a sense amplifier. The normal memory cell block includes a plurality of normal memory cells and a driving bit line connected to the normal memory cells. The reference memory cell block includes a reference bit line connected to a reference cell capacitor. The sense amplifier is configured to sense and amplify voltage levels of the driving bit line and the reference bit line.
Claims16
A semiconductor memory device having an open bit line structure, comprising:
- a normal memory cell block comprising a plurality of normal memory cells and a driving bit line connected to the normal memory cells;
- a reference memory cell block comprising a reference bit line connected to a reference cell capacitor;
- and
- a sense amplifier configured to sense and amplify voltage levels of the driving bit line and the reference bit line.
A semiconductor memory device having an open bit line structure, comprising:
- a plurality of normal memory cell blocks each comprising a plurality of normal memory cells and a driving bit line connected to the normal memory cells;
- first and second reference memory cell blocks disposed at opposite ends of the plurality of normal memory cell blocks, which are coupled in series, and each comprising reference bit lines connected to reference cell capacitors;
- and
- first and second sense amplifiers configured to sense and amplify voltage levels of the driving bit lines and voltage levels of reference bit lines.
A semiconductor memory device comprising:
- a plurality of normal memory cell blocks having an open bit line structure and comprising a plurality of memory cells, and bit lines and bit-bar lines connected to the memory cells;
- a reference memory cell block comprising reference bit lines connected to a plurality of reference memory cells;
- and
- a plurality of drivers configured to apply an activation voltage to the plurality of reference memory cells so that capacitances of reference cell capacitors included in the reference memory cells influence the voltage levels of the reference bit lines.
A semiconductor memory device comprising:
- a plurality of normal memory cell blocks having an open bit line structure and comprising a plurality of memory cells and bit lines and bit-bar lines connected to the memory cells;
- and
- a reference memory cell block comprising reference bit lines connected to a plurality of reference memory cells,
- wherein the reference bit lines are physically connected to reference cell capacitors included in the reference memory cells.
Dependencies are inferred from the claim text.