US 2011/0211406 A1Published application

Address delay circuit

AssigneeHynix Semiconductor Inc.

InventorsJae Bum KO, Jong Chern Lee

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Abstract

An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address.

Claims14

Dependent claims

An address delay circuit comprising:

a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output an external address as a first delayed address after a predetermined number of cycles of the first control clock;
a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as a second delayed address after a predetermined number of cycles of the second control clock;
and
a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address after a predetermined number of cycles of the clock elapse,
wherein the predetermined number of cycles of the clock is determined by output control signals.

2 more elements

Dependencies are inferred from the claim text.