External signal input circuit of semiconductor memory
AssigneeHynix Semiconductor Inc.
InventorJae Bum Ko
Life of this patent
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Abstract
In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.
Claims18
An external signal input circuit of a semiconductor memory, comprising:
- an input block configured to receive a plurality of external signals and to generate a plurality of internal signals;
- and
- a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.
An external signal input circuit of a semiconductor memory, comprising:
- a first input unit configured to receive a first external signal to generate a first internal signal;
- a second input unit configured to receive a second external signal to generate a second internal signal;
- a first control unit configured to receive the first internal signal and output the first internal signal;
- and
- a second control unit configured to block an output of the second internal signal based on a rank configuration of the semiconductor memory.
An external signal input circuit of a semiconductor memory, comprising:
- a first input unit configured to output a first buffering signal as a first internal signal, the first buffering signal being generated by receiving a first external signal;
- and
- a second input unit configured to select one of the first buffering signal and a second buffering signal, generated by receiving a second external signal, based on a rank configuration of the semiconductor memory and to output the selected buffering signal as a second internal signal,
- wherein the second input unit is configured to block an input of the second external signal based on the rank configuration.
Dependencies are inferred from the claim text.