Method of manufacturing a vertical-type semiconductor device and method of operating a vertical-type semiconductor device

A method of manufacturing a vertical-type semiconductor device, comprising:

• performing an isolation process on a substrate to form an isolation layer defining an active region and an isolation region in the substrate;
• forming a first impurity region in a surface of the substrate of the active region;
• forming a single-crystalline semiconductor pattern having a pillar shape on the active region of the substrate;
• forming a mask pattern on upper sidewalls of the single-crystalline semiconductor pattern, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern;
• forming a gate surrounding sidewalls of the single-crystalline semiconductor pattern, an upper surface of the gate making contact with a lower surface of the mask pattern, the gate having a linear shape;
• and
• forming a second impurity region under the upper surface of the single-crystalline semiconductor pattern;
• forming a bit line wiring electrically connected to the first impurity region;
• and
• forming a contact plug electrically connected to the second impurity region.

A method of operating a vertical-type semiconductor device including a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate extending to surround sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern and a second impurity region under the upper surface of the single-crystalline semiconductor pattern, comprising:

• applying a first voltage, a second voltage and a third voltage lower than the second voltage to the gate, the first impurity region and the second impurity region, respectively, such that poles are accumulated in the semiconductor pattern facing with the gate to input programming data;
• applying a fourth voltage, and a fifth voltage and a sixth voltage having the opposite polarity to the fourth voltage to the gate, the first impurity region and the second impurity region, respectively, such that poles are removed from the semiconductor pattern facing with the gate to input erasing data;
• and
• applying seventh and eighth voltages to the gate and the first impurity region, respectively, to read the stored data.