Field effect transistors for a flash memory comprising a self-aligned charge storage region
AssigneeGlobalfoundries Inc.
InventorsThilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
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Abstract
Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.
Claims20
A non-volatile storage transistor, comprising:
- a gate electrode formed above a semiconductor region and separated therefrom by a gate insulation layer;
- a source region formed in said semiconductor region and connecting to a channel region at a source side of said storage transistor;
- a drain region formed in said semiconductor region and connecting to said channel region at a drain side of said storage transistor;
- a floating sidewall spacer formed at a sidewall of said gate electrode at least at said drain side of said storage transistor, said floating sidewall spacer being formed above a portion of said channel region and above a portion of said drain region;
- a first dielectric layer formed so as to separate said floating sidewall spacer from said gate electrode;
- and
- a second dielectric layer formed so as to separate said floating sidewall spacer from said channel region and said drain region.
A method of storing information in a non-volatile storage transistor, the method comprising:
- providing a charge storage region adjacent to and electrically insulated from a drain region and a gate electrode of said storage transistor, said charge storage region being positioned to influence charge flow in a channel region of said storage transistor;
- and
- applying a programming voltage between said gate electrode and said drain region of said storage transistor so as to initiate charge carrier transfer from said gate electrode to said charge storage region.
A method of forming a non-volatile storage transistor, the method comprising:
- forming a gate electrode structure on a semiconductor region;
- and
- forming a dielectric charge storage region in a self-aligned manner adjacent to and electrically insulated from a channel region and a drain region of said storage transistor.
Dependencies are inferred from the claim text.