US 2011/0211390 A1Published application

Semiconductor device and its manufacturing method

AssigneeRenesas Technology Crop.

InventorsSatoru Hanzawa, Fumihiko Nitta, Nozomu Matsuzaki, Toshihiro Tanaka

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Abstract

A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Claims12

Dependent claims

A semiconductor device comprising:

a plurality of word lines;
a plurality of bit-lines intersecting the plurality of word lines;
a plurality of memory cells arranged at intersection points of the plurality of word lines and the plurality of bit-lines;
a block of word drivers for controlling the plurality of word lines;
a sense amplifier for discriminating read signals generated in the plurality of bit-lines;
a first voltage supply line arranged in parallel with the plurality of bit-lines;
a first plurality of buffer cells which are arranged at intersection points of the plurality of word lines and the first voltage supply line and are not connected to the first voltage supply line;
a second voltage supply line arranged in parallel with the plurality of word lines;
and
a second plurality of buffer cells which are arranged at intersection points of the plurality of bit-lines and the second voltage supply line and are not connected to the plurality of bit-lines, wherein
the first plurality of buffer cells are arranged between the block of word drivers and the plurality of memory cells,
the second plurality of buffer cells are arranged between the sense amplifier and the plurality of memory cells, and
each of the plurality of memory cells includes a first resistive storage element and a first select transistor.

10 more elements

Dependencies are inferred from the claim text.