Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors

A memory cell, comprising:

• a storage element comprising first and second NFETs and first and second PFETs, wherein the source terminals of each NFET are coupled to a ground potential and the source terminals of each PFET are coupled to a first potential, wherein the gate terminal of the first NFET is coupled to the gate terminal of the first PFET, wherein the gate terminal of the second NFET is coupled to the gate terminal of the second PFET, wherein the drain terminal of the first NFET is coupled to the drain terminal of the first PFET, wherein the drain terminal of the second NFET is coupled to the drain terminal of the second PFET, and wherein the gate terminals of the first NFET and first PFET are coupled to the drain terminals of the second NFET and second PFET and the gate terminals of the second NFET and second PFET are coupled to the drain terminals of the first NFET and the first PFET;
• a write circuit comprising third and fourth NFETs, wherein the gate terminals of the third and fourth NFETs are coupled together and are adapted to be coupled to a write word line, wherein the source terminals of the third and fourth NFETs are each adapted to be coupled to one of a pair of complementary bit lines, wherein the drain terminal of the third NFET is coupled to the gate terminals of the first NFET and first PFET, and wherein the drain terminal of the fourth NFET is coupled to the gate terminals of the second NFET and second PFET;
• and
• a read circuit comprising fifth and sixth NFETs, wherein the source terminal of the fifth NFET is coupled to the ground potential, wherein the gate terminal of the fifth NFET is coupled to the drain terminals of the first NFET and first PFET, wherein the drain terminal of the fifth NFET is coupled to the source terminal of the sixth NFET, wherein the gate terminal of the sixth NFET is adapted to be coupled to a read word line, and wherein the drain terminal of the sixth NFET is adapted to be coupled to a read bit line.

A memory cell, comprising:

• means for storing data;
• means for writing data into the means for storing data, the means for writing data coupled to the means for storing data;
• and
• means for reading data from the means for storing data, the means for reading data being coupled to the means for storing data;
• wherein at least a portion of the means for storing data and at least a portion of the means for writing data are fabricated using a thicker functional gate oxide and at least a portion of the means for reading data is fabricated using a thinner functional gate oxide.

A memory array comprising a plurality of memory cells, wherein at least one memory cell comprises:

• a storage element;
• a write circuit coupled to the storage element;
• and
• a read circuit coupled to the storage element;
• wherein at least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.