Static random-access memory with boosted voltages

Circuitry comprising:

• address register circuitry operable to generate a word line signal;
• a word line;
• a plurality of memory elements coupled to the word line, wherein the word line is operable to convey the word line signal to the plurality of memory elements and wherein each of the memory elements of the plurality of memory elements comprises a power supply terminal;
• and
• switching circuitry operable to selectively couple the power supply terminals of the plurality of memory elements to a first power supply line at a first voltage during memory read operations and to selectively couple the power supply terminals of the plurality of memory elements to a second power supply line at a second voltage during memory write operations, wherein the first voltage is different than the second voltage.

A method comprising:

• generating a word line signal;
• conveying the word line signal over a word line to a plurality of memory elements, wherein each of the memory elements of the plurality of memory elements comprises a power supply terminal;
• during memory read operations, selectively coupling the power supply terminals of the plurality of memory elements to a first power supply line at a first voltage;
• and
• during memory write operations, selectively coupling the power supply terminals of the plurality of memory elements to a second power supply line at a second voltage, wherein the first voltage is greater than the second voltage.