Clock generation circuit and integrated circuit

An image sensing apparatus comprising a clock generation circuit that generates and outputs first and second clocks that have a non-overlap period with respect to an external clock, and a pixel array having a plurality of pixels and configured to operate in accordance with the first and second clocks, the clock generation circuit comprising:

• a first generation unit including a first delay element, that generates, by causing the external clock to pass through the first delay element, the first clock that has a first delay time depending on a propagation delay time of the first delay element relative to the external clock, and outputs the generated first clock;
• a second generation unit including a second delay element, that generates, by causing the external clock to pass through the second delay element, the second clock that has a second delay time depending on a propagation delay time of the second delay element relative to the external clock, and outputs the generated second clock;
• and
• a control unit including a plurality of third delay elements, that generates a control signal for controlling the third delay elements such that a total of propagation delay times caused by the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock by causing the external clock to pass through the plurality of third delay elements, and controls, by supplying the control signal to the first delay element, the second delay element, and the plurality of third delay elements, respectively, the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay time of the third delay element.

An image sensing apparatus comprising a clock generation circuit that generates and outputs first and second clocks that have a non-overlap period with respect to an external clock, and a pixel array having a plurality of pixels and configured to operate in accordance with the first and second clocks, the clock generation circuit comprising:

• a first generation unit including a first delay element, that generates, by causing the external clock to pass through the first delay element, the first clock that has a first delay time depending on a propagation delay time of the first delay element relative to the external clock, and outputs the generated first clock;
• a second generation unit including a second delay element, that generates, by causing the external clock to pass through the second delay element, the second clock that has a second delay time depending on a propagation delay time of the second delay element relative to the external clock, and outputs the generated second clock;
• and
• a control unit including a plurality of third delay elements, that oscillates at a frequency depending on a total of propagation delay times caused by the plurality of third delay elements so as to generate a third clock, generates a control signal for controlling the third delay elements such that the total of the propagation delay times of the plurality of third delay elements corresponds to a target value depending on a cycle of the external clock by comparing a phase of a frequency division clock obtained by dividing a frequency of the generated third clock with a phase of the external clock, and controls, by supplying the control signal to the first delay element, the second delay element, and the plurality of third delay elements, respectively, the propagation delay time of the first delay element, the propagation delay time of the second delay element, and the propagation delay time of the third delay element.