Dynamic-to-static converter latch with glitch suppression

A circuit comprising:

• a precharge transistor coupled between a voltage supply node and a precharge node and configured to precharge the precharge node during a first phase of a clock signal;
• an input circuit coupled to receive an input data signal and configured to convey, based on a state of the input data signal, a first logic state to the precharge node during a second phase of the clock signal;
• and
• an evaluation circuit including:
• a second pull-up transistor coupled between the supply voltage node and a transfer node and having a gate terminal coupled to the precharge node;
• a discharge circuit including a first discharge transistor and a second discharge transistor;
• and
• a delay circuit coupled to receive the clock signal and configured to delay the clock signal by a delay time;
• wherein the first discharge transistor is configured to activate responsive to the clock signal transitioning to the second phase, wherein the second discharge transistor is configured to activate at the delay time subsequent to the to the clock signal transitioning to the second phase, wherein the evaluation circuit is configured to convey a second logic state to the transfer node responsive to at least the clock signal transitioning to the second phase.

A dynamic-to-static latch circuit comprising:

• a dynamic circuit including an input transistor and a precharge transistor each coupled to a first data node, wherein the precharge transistor is configured to precharge the first data node during a first phase of a clock signal and wherein the input transistor is configured to convey a first logic value to the first data node;
• a transition circuit configured to convey a second logic value to a second data node during an evaluation phase that is concurrent with a second phase of the clock signal, the transition circuit including a pull-up transistor, a pull-down transistor, and a discharge circuit, wherein the discharge circuit is configured to be active during the evaluation phase, the evaluation phase beginning at a delay time subsequent to entering the second phase of the clock signal and terminating upon completion of the second phase of the clock signal;
• and
• a static circuit configured to store the second logic value on the second data node subsequent to termination of the evaluation phase.

A register file comprising:

• a plurality of storage cells;
• at bit line coupled to one or more of the plurality of storage cells;
• and
• a latch circuit coupled to receive a bit from the bit line, the latch circuit including:
• a precharge circuit configured to precharge the first node during a first phase of a clock signal;
• an input circuit coupled to receive a bit having a first logic value to be written to one of the plurality of cells, wherein the input circuit is coupled between an input node and a first node, wherein the input circuit is configured to drive a signal having a second logic value onto the first node during a second phase of the clock signal;
• a transfer circuit configured to, drive a signal having the first logic value onto a second node during an evaluation phase that is concurrent with the second phase of the clock signal, the evaluation phase beginning at a delay time subsequent to a beginning of the second phase of the clock signal and completing at an end of the second phase of the clock signal;
• and
• an output circuit coupled to circuit coupled to the transfer circuit and configured to drive an output signal at the first logic value onto the bit line responsive to the transfer circuit driving the signal at the first logic value onto the second node during the evaluation phase.

An integrated circuit comprising:

• at least one dynamic logic circuit;
• at least one static logic circuit, and at least one dynamic-to-static converter circuit coupled between the dynamic logic circuit and the static logic circuit, the dynamic-to-static converter circuit including:
• a dynamic circuit having a precharge transistor configured to precharge a first node during a first phase of a clock signal, and an input transistor coupled to receive a logic signal at a first logic value and configured to drive the first node to a second logic value during a second phase of the clock signal;
• a transition circuit configured to drive the first logic value onto a second node during an evaluation phase concurrent with the second phase of the clock signal, wherein the evaluation phase begins at a delay time subsequent to entering the second phase of the clock signal and terminating at an end of the second phase of the clock signal;
• and
• a storage circuit configured to store the first logic value on the second node and the second logic value on a third node subsequent to terminating the evaluation phase.