Apparatus and method for providing multi-mode clock signals
AssigneeAnalog Devices, Inc.
InventorJohn Kevin Behel
Life of this patent
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Abstract
Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished.
Claims21
An apparatus comprising:
- a multi-mode driver configured to receive a first clock signal, and to generate a second clock signal at least partly in response to the first clock signal;
- and
- a circuit of the multi-mode driver that is configured to determine output characteristics of the second clock signal such that the second clock signal is in compliance with a selected one of a plurality of different standards, wherein the characteristics are determined based at least partly on one or more control signals provided to the circuit, wherein the first clock signal has a characteristic other than the selected standard,
- wherein the plurality of different standards comprise one or more of:
- the low voltage differential signaling (LVDS) standard,
- the positive emitter-coupled logic (PECL) standard,
- the low-voltage positive emitter-coupled logic (LVPECL) standard,
- the complementary metal-oxide-semiconductor (CMOS) standard, or
- the High-Speed Transceiver Logic (HSTL) standard.
An apparatus comprising:
- an H-bridge configured to receive a first clock signal and to generate a second clock signal as an output;
- a first circuit comprising a first switch, the first circuit in electrical communication with the H-bridge;
- a second circuit comprising a second switch, the second circuit in electrical communication with the H-bridge;
- wherein the first clock signal switches between a first set of voltage levels, and wherein the second clock signal switches between a second set of voltage levels, the second set of voltage levels different from the first set of voltage levels.
An apparatus for converting clock signals, the apparatus comprising:
- an H-bridge electrically connected with a channel, the H-bridge comprising a first, second, third, and fourth transistor;
- an operational amplifier configured to amplify a voltage having an output electrically connected to a fifth transistor;
- and
- means for providing a bias current electrically connected to a sixth transistor;
- wherein the H-bridge is configured to receive a first clock signal and to output a second clock signal on the channel, and wherein the second clock signal is compliant with a logic standard and the first clock signal is not compliant with the logic standard.
A method of converting a clock signal, the method comprising:
- providing an H-bridge electrically connected with a channel, the H-bridge comprising a first, second, third, and fourth transistor;
- providing an operational amplifier having an output electrically connected to a fifth transistor;
- and
- providing a bias current source control electrically connected to a sixth transistor;
- adjusting a common mode voltage with the operational amplifier;
- controlling a first current using the bias current source control,
- using the H-bridge to receive a first clock signal and to generate a second clock signal, wherein levels of the second clock signal are based at least partly on the first current.
Dependencies are inferred from the claim text.