Delta phi generator with start-up circuit
AssigneeFreescale Semiconductor, Inc.
InventorJohn M. Pigott
Life of this patent
Estimating the term…
Abstract
A circuit comprises a delta phi generator, a startup circuit, and a level detector. The delta phi generator has a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state. The startup circuit is coupled to the delta phi generator. The startup circuit ensures that the delta phi generator does not operate in the undesirable operating state. The level detector comprises a comparator with an offset. The comparator has a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit. The level detector detects the delta phi voltage, and in response, disables the startup circuit.
Claims20
A circuit comprising:
- a delta phi generator having a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state;
- a startup circuit coupled to the delta phi generator, the startup circuit for ensuring the delta phi generator does not operate in the undesirable operating state;
- and
- a level detector comprising a comparator with an offset, the comparator having a first input coupled to the output node, a second input coupled to a reference voltage, and an output coupled to the startup circuit, the level detector for detecting the delta phi voltage, and in response, disabling the startup circuit.
A circuit comprising:
- a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode and a second current electrode coupled together;
- a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode;
- a resistive element having a first terminal coupled to the second current electrode of the second transistor, and a second terminal coupled to a second power supply voltage terminal;
- a third transistor having a first current electrode coupled the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode of the second transistor;
- a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to the second power supply voltage terminal;
- a startup circuit coupled to provide a current to the control electrodes of the second and fourth transistors during power up of the circuit;
- and
- a level detector comprising a comparator with an offset, the comparator having a first input coupled to the first terminal of the resistive element, a second input coupled to the second terminal of the resistive element, and an output coupled to the startup circuit, the level detector for disabling the startup circuit in response to detecting a predetermined voltage difference between the first and second inputs.
A circuit comprising:
- a delta phi generator having a desirable operating state for developing a delta phi voltage at an output node in response to an input voltage, and an undesirable operating state;
- a startup circuit coupled to the delta phi generator, the startup circuit for ensuring the delta phi generator does not operate in the undesirable operating state;
- and
- a level detector comprising a comparator with an offset, the comparator comprising:
- a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
- a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the output node of the delta phi generator, and a second current electrode;
- a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal;
- a fourth transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second power supply voltage terminal, a second current electrode coupled to the control electrode of the third transistor;
- and
- a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the first current electrode of the fifth transistor and to the control electrode of the third transistor, and a second current electrode coupled to the second power supply voltage terminal.
Dependencies are inferred from the claim text.