Receiving circuit and receiving system

A receiving circuit for selectively receiving one pair of a plurality of pairs of input signals, comprising:

• a plurality of input buffer circuits, each supplied with one pair of the pairs of input signals and each being switchable between an output mode and a cutoff mode, each of the input buffer circuits supplying, in the output mode, to a pair of common nodes a pair of current signals corresponding to the pair of input signals supplied to that input buffer circuit, and stopping the supply of the pair of current signals in the cutoff mode;
• and
• an output circuit configured to convert the pair of current signals supplied to the pair of common nodes into a pair of voltage signals,
• wherein each of the input buffer circuits includes
• a first constant current generation section configured to generate, in the output mode, a pair of constant currents in a pair of current paths going from a pair of intermediate nodes to a first reference node, and stopping the generation of the pair of constant currents in the cutoff mode, the pair of intermediate nodes being connected with the pair of common nodes;
• a voltage-to-current conversion section configured to generate, in the output mode, a pair of input currents corresponding to the pair of input signals supplied to that input buffer circuit in a pair of current paths going from the pair of intermediate nodes to a second reference node to thereby generate the pair of current signals in a pair of current paths going from the pair of intermediate nodes to the pair of common nodes, and stopping the generation of the pair of input currents in the cutoff mode;
• and
• a pair of input transistors formed in the pair of current paths going from the pair of intermediate nodes of that input buffer circuit to the pair of common nodes, the pair of input transistors having a pair of gates to which a first bias voltage is supplied,
• wherein the output circuit includes
• a second constant current generation section configured to generate a pair of constant currents in a pair of current paths going from the pair of common nodes to the second reference node;
• a pair of output transistors formed in a pair of current paths going from a pair of output nodes to the pair of common nodes, and having a pair of gates to which a second bias voltage is supplied, the pair of output nodes being configured to output the pair of voltage signals;
• and
• a pair of load resistors formed in a pair of current paths going from the pair of output nodes to a third reference node.