Resonant Clock And Interconnect Architecture For Digital Devices With Multiple Clock Networks
AssigneeCyclos Semiconductor, Inc.
InventorsAlexander T. Ishii, Marios C. Papaefthymiou
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Abstract
A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
Claims26
A system comprising:
- a semiconductor device comprising a set of configurable components, each of the set of configurable components comprising a first configuration and a second configuration;
- a clock generator configured to provide a resonant high-speed clock signal of frequency f to a first configurable component and a second configurable component of the set of configurable components;
- and
- a signal network configured to provide a set of enablement signals, at least one of the set of enablement signals being provided to the first configurable component to switch the first configurable component from the first configuration to the second configuration to provide a derived clock signal based on the resonant high-speed clock signal from the first configurable component at a frequency different from the frequency f and at least another of the set of enablement signals being provided to the second configurable component to switch the second configurable component from the first configuration to the second configuration to provide a derived clock signal based on the resonant high-speed clock signal from the second configurable component at a frequency different from frequency f.
A system, comprising:
- a programmable logic device (PLD) comprising a set of storage devices;
- a clock generator configured to provide a resonant high-speed clock signal of frequency f to a first storage device of the set of storage devices and to a second storage device of the set of storage devices;
- and
- a signal network configured to provide a set of enablement signals, each of the set of enablement signals being provided to at least one of the set of storage devices to configure the at least one of the set of storage devices to function based on the resonant high-speed clock signal at a frequency different from frequency f.
A system, comprising:
- means for providing a resonant high-speed clock signal of frequency f to each of a set of storage devices in a programmable logic device;
- and
- means for providing a plurality of enablement signals, wherein each of the plurality of enablement signals is provided to at least one of the set of storage devices to configure the at least one of the set of storage devices to function based on the resonant high-speed clock signal at a frequency different from the frequency f.
Dependencies are inferred from the claim text.