US 2011/0210444 A1 · 3D Semiconductor Package Using An Interposer

Abstract

A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

Claims20

Dependent claims

A semiconductor device comprising:

a first die;
a second die;
an interposer, the first die being electrically coupled to a first side of the interposer, the second die being electrically coupled to a second side of the interposer;
and
a substrate, the substrate being electrically coupled to the second side of the interposer, wherein the substrate includes a cavity, the second die being positioned within the cavity.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/813,212Filed 10 Jun 2010

Priority

26 Feb 2010

Published

1 Sep 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 90/00
Package configurations
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
H10W 20/0249
The interconnections being through-semiconductor vias: wherein the through-semiconductor via protrudes from backsides of the chips, wafers or…
H10W 70/635
Vias, e.g. via plugs: through-vias

3D Semiconductor Package Using An Interposer

Life of this patent

3D Semiconductor Package Using An Interposer

Life of this patent

Abstract

Claims20