Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof

A trace substrate for carrying a chip, wherein the trace substrate comprises:

• a plurality of traces;
• a plurality of conductive studs correspondingly formed on the traces;
• a plurality of traces pad correspondingly disposed on the traces, wherein each trace pad and each conductive stud are separated by a distance along an extending direction of the traces;
• and
• a trace modling compound for encapsulating the conductive studs and the traces and exposing a conductive stud surface of each conductive stud and a trace surface of each trace.

A semiconductor package method for manufacturing, comprising:

• providing a carrier;
• forming a plurality of traces on a lower surface of the carrier;
• forming a plurality of traces pads on the traces, wherein each trace pad and each conductive stud are separated by a distance along an extending direction of the traces;
• forming a plurality of conductive studs on the traces;
• encapsulating the conductive studs and the traces by a trace modling compound;
• grinding the bottom surface of the trace modling compound to expose a conductive stud surface of each conductive stud;
• removing the carrier to expose a trace surface of each trace, so that the conductive studs, the traces and the trace modling compound form a trace substrate;
• disposing a chip on the trace substrate;
• correspondingly electrically connecting the chip and the traces via a plurality of wires;
• forming a chip modling compound on the trace substrate, wherein the chip modling compound encapsulates the chip and the wires.

A trace substrate method for manufacturing, comprising:

• providing a carrier;
• forming a plurality of traces on a lower surface of the carrier;
• forming a plurality of conductive studs in the traces;
• forming a plurality of traces pads in the traces, wherein each trace pad and each conductive stud are separated by a distance along an extending direction of the traces;
• encapsulating the conductive studs and the traces by a trace modling compound;
• grinding the bottom surface of the trace modling compound to expose a conductive stud surface of each conductive stud;
• and
• removing the carrier to expose a trace surface of each trace.